1. Field of the Invention
The invention relates to a semiconductor device manufacturing method, particularly, a method of manufacturing a semiconductor device where a split-gate type nonvolatile memory transistor and a MOS transistor are formed on the same substrate.
2. Description of the Related Art
In recent years, an electrically programmable and erasable read-only memory device (hereafter, referred to as EEPROM) has been broadly used as a flash memory, together with the expansion of its application field such as cellular phones or digital cameras.
The EEPROM stores binary or multivalued digital data depending on whether a predetermined amount of electric charge is accumulated in a floating gate, and reads out the digital data by detecting a conductance change in a channel region corresponding to the amount of the electric charge.
This EEPROM includes a stacked-gate type having a structure where a floating gate and a control gate are stacked in this order on a semiconductor substrate and a split-gate type having a structure where a floating gate and a control gate face the channel region of a semiconductor substrate.
FIG. 6 shows a cross-sectional view of a split-gate type memory transistor 100 as the general structure of the EEPROM.
Hereafter, the structure of the split-gate type memory transistor 100 will be described. An n+ type drain region 102 and an n+ type source region 103 are formed on the front surface of a P-type semiconductor substrate 101 at a predetermined distance from each other, and a channel region 104 is formed therebetween. A floating gate 106 is formed on a part of this channel region 104 and a part of the source region 103 with a gate insulation film 105 interposed therebetween. A thick silicon oxide film 107 is formed on the floating gate 106.
A tunnel insulation film 108 is formed so as to cover the side of the floating gate 106 and a portion of the upper surface of the silicon oxide film 107. A control gate 109 is formed on the tunnel insulation film 108 and a portion of the channel region 104.
The memory transistor of the split-gate type EEPROM is described in Japanese Patent Application Publication No. Hei 11-284083.
Processes for forming a nonvolatile memory transistor and a MOS transistor on the same semiconductor substrate are simplified as much as possible. For example, when the memory transistor and the MOS transistor are formed on the same semiconductor substrate, generally, an insulation film to be the tunnel insulation film of the memory transistor and an insulation film to be the gate insulation film of the MOS transistor are formed in the same process. This technology is described in Japanese Patent Application Publication No. Hei 11-111936.
It is necessary to provide desired performance to each of the memory transistor and the MOS transistor when these are formed on the same semiconductor substrate. Thus, taking account of the operational characteristics of the memory transistor (a threshold voltage or a memory current value), it is difficult to set the breakdown voltage of the MOS transistor to about 12V or more. In the conventional manufacturing method, as described above, the manufacturing the tunnel insulation film and the gate insulation film of the MOS transistor in the same process is desirable for the simplicity of the manufacturing process, but making the thickness of the gate insulation film large in order to provide the MOS transistor with a high breakdown voltage makes the thickness of the tunnel insulation film of the memory transistor too large, thereby degrading the operational characteristics of the memory cell. Concretely, the semiconductor device has a tunnel insulation film and a gate insulation film having a thicknesses of about 22 nm.
However, recently, the systems where the above described EEPROM is equipped on a logic IC, a microcomputer, or the like have been developed, and there is sometimes the case of providing a circuit operating at a higher power supply voltage (e.g. 25V) therein. Therefore, according to such a higher power supply voltage, there has been a need to form the MOS transistor having a higher breakdown voltage on the same semiconductor substrate.